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CS704 – Advanced Computer Architecture-II

In CS704 Advanced Computer Architecture-II we have you covered with Digitized Past Papers From Fall of Mid Term and Final Term.

NOTE: Click on Preparation Tab to take the MCQ’s Tests.

FINAL TERM
CS704_Final Term Solutions by ashiq                                  View     Download
CS704_finalterm_QA_Past Papers                                       View     Download
MID TERM
CS704 – Solution of most Important Questions                     View     Download

1 Comment

  1. AYESHA MUMTAZ

    Long Questions:
    Q.1.Find the die yield for a processor chip with the following manufacturing cost factors: die size = 380 mm
    2
    , estimated defect rate = 0.75 per cm
    2
    , α = 4 (5)
    Solutions:
    Die yield is the fraction or percentage of good dies on a wafer number • Wafer yield accounts for completely bad wafers so need not be tested
    • Wafer yield corresponds to on defect density by α which depends on
    number of masking levels
    • Good estimate for CMOS is 4.0 and
    • Die yield = Wafer yield x (1 + defects per unit area x die area)/ α) –α
    • Example: The yield of a die, 0.7cm on a side, with defect density of 0.6/cm
    2 = (1+[0.6×0.47]/4.0) -4 = 0.75
    Die yield = Wafer yield x (1 + defects per unit area x die area / α) ) –α
    Example: The yield of a die, 0.7cm on a side, with defect density of 0.75/cm
    2
    So, = (1+[0.75 x 380]/4.0) -4 = (1+285 / 4 ) -4
    (71.5) -4 = 1
    / (71.5 ) 4 = 0.00349
    Q.2. If computer A runs a programs in 5seconds and computer B runs the same program in 10 seconds, how much
    slower is B than A? RR=3 (5)
    Q.4. Briefly define the following terms: (10)
    Pipelining:
    A technique used in advanced microprocessors where the microprocessor begins executing a
    second instruction before the first has been completed. That is, several instructions are in the
    pipeline simultaneously, each at a different processing stage.
    The pipeline is divided into segments and each segment can execute its operation concurrently with the other
    segments. When a segment completes an operation, it passes the result to the next segment in the pipeline and
    fetches the next operation from the preceding segment. The final results of each instruction emerge at the end of
    the pipeline in rapid succession.

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